The present invention relates to a buffer memory, a method and a buffer controller for queue management, and more particularly, to a buffer memory usable in an ATM switch and having only one read and one write port.
It is generally desirable to achieve a high frequency throughput of data cells in a buffer memory. However, for reasons of keeping the complexity of such a memory moderate, it is desirable to limit the number of ports of the memory. A memory with only one read port and one write port allows one read operation and one write operation per cycle which implies that the memory itself is required to operate at a high frequency in order to manage the high bandwidth. This requires the buffer memory to be pipelined.
An object of the present invention is to enable a high frequency output in a pipelined buffer memory with only one read and write per cycle, by means of free-queues and a tailored queue management algorithm. The relation between the pipelining of the memory and the number of free queues is such that there is one additional free-queue per pipeline stage in the buffer. This object is achieved by means of a buffer memory, a method for queue management and a buffer controller.
The above object is achieved by means of a buffer memory, a method for queue management and a buffer controller as claimed in claims 1, 7 and 10, respectively.
Using high operating frequencies means that it is necessary to pipeline the reading. In a preferred embodiment of the invention this pipelining is enabled by using two free-queues, that is one queue is working while the other is updated.